Seasoned industry expert in RTL design & verification for Low Power SOCs
Good Coding Practices for Race-Free Designs and Predictable Synthesis
Unified Verification Methodology (UVM)
Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) Strategies to Prevent Metastability
Formal Verification - Where it works and How-To Code Assertions for Formal
Unified Power Format (UPF) - Designing an Implementable Low Power Strategy
Early Power Estimation - Obtaining Highly Correlated Accurate Power Estimation
Safety Considerations for Automotive Designs (ISO 26262)
Design RTL and Testbenches which works on all major EDA tools
Increase confidence level by complementing your dynamic simulation with Lint, CDC, Formal & Fault Injection
Understand how RTL architectural & design decisions affect implementation flow - reducing TAT and improving performance
We always start with a client discovery to tailor our trainings to your skill level and bring it up to the next.
Speed up your verification process by utilizing our quality proven AMBA VIPs.
AMBA APB3 Verilog VIP
AMBA AHB5 Verilog VIP
AMBA AXI4 Verilog VIP
ARM CM7 TCM Verilog VIP
Digital solutions for your business.
Website design with Google Analytics & Shutterstock Photos
Setup of online payment portals
Automate business leads, HR processes, payroll, CPF contribution and tax forms.
Local entity registration & setup expertise.
Leverage our expertise in setting up multiple semiconductor start ups in Singapore & Malaysia.
Tap onto our network of local engineering resources with proficiency in English & Chinese language.
A proudly local Singaporean company.
UEN: 202203126K
Contact info@techbuddy.com.sg to get more information about our professional training courses.