Unlimited instances.

Supports sending all types of APB3 stimulus.

Support APB master and slave

Ease of control for sending APB in any timing sequences (as APB master)

Provides complete configuration parameters to control APB VIP.

RAL-ready where adaptor and predictor are built-in and ready to pair with user’s regmodel.

API-based reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers.

Comes with complete Compliance and Regression testsuite to verify APB slave memory, protocol checks, out of bound memory access etc

On-the-fly protocol and data integrity checking.

Useful signals and events at waveforms for high debug-ability like packet counter, output sampling, signal enums etc

Comprehensive tracker log for APB bus activities including byte address activity tracker.

End of test memory printing and bus activity statistic summary.

Fully parameterizable signal widths.

Includes Reference Verification testbench for easy integration, configuration and setup.

Includes sample scoreboard to fetch sequence item from the UVC.

Setup and hold verification by clocking block mechanism and X injection.

Unlimited instances.

Supports sending all types of AXI stimulus for AXI3, AXI4, AXI4-Lite, including low power features.

Support AXI master and slaves

Ease of control for sending AXI in AW, W, AR channels in any timing sequences (as AXI master), including injecting delays or in concurrent sending.

Provides complete configuration parameters to control AXI VIP.

Timeout mechanism while waiting ready signal

RAL-ready where adaptor and predictor are built-in and ready to pair with user’s regmodel.

Provide API for register partial access verification (byte and hword accesses), in compliment for bit-bashing verification by UVM.

API-based reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers.

Comes with complete Compliance and Regression testsuite to verify AXI slave memory, outstanding transaction threshold, protocol checks, out of bound memory access etc

Integrated ARM AXI SVA embedded for protocol compliance check with assertion coverage.

On-the-fly protocol and data integrity checking.

Performance checking for wait latency.

Useful signals and events at waveforms for high debug-ability like packet counter, effective address, effective data, corresponding ID etc

Comprehensive tracker log for AXI bus activities including byte address activity tracker.

End of test memory printing and bus activity statistic summary.

Fully parameterizable signal widths.

Includes Reference Verification testbench for easy integration, configuration and setup.

Includes sample scoreboard to fetch sequence item from the UVC.

Setup and hold verification by clocking block mechanism and X injection.

Unlimited instances.

Supports sending all types of AHB stimulus for AHB4 and AHB5.

Supports cancel packet scenario while bad HRESP, idle, busy etc injection into AHB traffic.

Support AHB master and slaves

Ease of control for sending AHB in any timing sequences (as AHB master), in pipelined or waited mode.

Provides complete configuration parameters to control AHB VIP.

RAL-ready where adaptor and predictor are built-in and ready to pair with user’s regmodel.

Provide API for register partial access verification (byte and hword accesses), in compliment for bit-bashing verification by UVM.

API-based reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers.

Comes with complete Compliance and Regression testsuite to verify AHB slave memory, protocol checks, out of bound memory access etc

Integrated ARM AHB SVA embedded for protocol compliance check with assertion coverage.

On-the-fly protocol and data integrity checking.

Useful signals and events at waveforms for high debug-ability like packet counter, output sampling, signal enums etc

Comprehensive tracker log for AHB bus activities including byte address activity tracker.

End of test memory printing and bus activity statistic summary.

Fully parameterizable signal widths.

Includes Reference Verification testbench for easy integration, configuration and setup.

Includes sample scoreboard to fetch sequence item from the UVC.

Setup and hold verification by clocking block mechanism and X injection.

Unlimited istances.

Supports sending all types of TCM stimulus.

Supports cancel packet scenario while WAIT.

Support TCM master and slave

Ease of control for sending TCM in any timing sequences (as TCM master), in pipelined or waited mode.

Provides complete configuration parameters to control TCM VIP including behavior in ecc enabled TCM, chance to cancel packet etc.

API-based reset-aware UVM Component which is user friendly for non UVM experienced engineers and designers.

Comes with complete Compliance and Regression testsuite to verify TCM slave memory, protocol checks, out of bound memory access etc

On-the-fly protocol and data integrity checking.

Useful signals and events at waveforms for high debug-ability like packet counter, output sampling, signal enums etc

Comprehensive tracker log for TCM bus activities including byte address activity tracker.

End of test memory printing and bus activity statistic summary.

Fully parameterizable signal widths.

Includes Reference Verification testbench for easy integration, configuration and setup.

Includes sample scoreboard to fetch sequence item from the UVC.

Setup and hold verification by clocking block mechanism and X injection.